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2003-02-25a 1/32 t c 5 8 n v g 0 s 3 a f t 0 0 tentative toshiba mos digital integrated circuit silicon gate cmos 1gbit (128m u 8bits) cmos nand e 2 prom description the tc58nvg0s3a is a single 3.3-v 1g-bit (1,107 ,296,256 bits) nand elec trically erasable and programmable read-only memory (nand e 2 prom) organized as (2048+64) bytes x 64 pages x 1024 blocks. the device has a 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. the erase operation is implemented in a single block unit (128 kbytes + 4kbytes: 2112 bytes x 64 pages). the tc58nvg0s3a is a serial-type memory device which utilizes the i/o pins for both address and data input / output as well as for command inputs. the erase and program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non- volatile memory data storage. features x organization memory cell allay 2112 u 64k u 8 register 2112 u 8 page size 2112bytes block size (128k 4k) bytes x modes read 9? reset 9? auto page program auto block erase 9? status read x mode control serial input 9? output command control pin assignment (top view) pin names i/o1 to i/o8 i/o port ce chip enable we write enable re read enable cle command latch enable ale address latch enable wp write protect by / ry ready / busy gnd ground input v cc power supply v ss ground x toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in ge neral can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to a void situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage t o property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de fo r semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. x the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction o r failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy con trol instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control inst ruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be m ade a t the customer?s own risk. 000707eba1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 nc nc nc nc i/o8 i/o7 i/o6 i/o5 nc nc nc v cc v ss nc nc nc i/o4 i/o3 i/o2 i/o1 nc nc nc nc nc nc nc nc nc gnd nc nc v cc v ss nc nc cle ale nc nc nc nc nc we by / ry 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 wp re ce x powersupply v cc 2.7 v to 3.6 v x program/erase cycles 1e5 cycles(with ecc) x access time cell array to register 25 p s max serial read cycle 50 ns min x operating current read (50 ns cycle) 10 ma typ. program (avg.) 10 ma typ. erase (avg.) 10 ma typ. standby 50 p a max x package tsop i 48-p-1220-0.50 (weight : 0.53 g typ.) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 2/32 t c 5 8 n v g 0 s 3 a f t 0 0 block diagram absolute maximum ratings symbol rating value unit v cc power supply voltage 0.6 to 4.6 v v in input voltage 0.6 to 4.6 v v i/o input /output voltage 0.6 v to v cc 0.3 v ( ? 4.6 v) v p d power dissipation 0.3 w t solder soldering temperature (10s) 260 c t stg storage temperature -55 to 150 c t opr operating temperature 0 to 70 c capacitance * (ta 25c, f 1 mhz) symb0l parameter condition min max unit c in input v in 0 v 10 pf c out output v out 0 v 10 pf * * this parameter is periodically sampled and is not tested for every device. i/o control circuit status register address register command register column buffer column decoder data register sense amp memory cell array control circuit hv generator row address decorder logic control by / ry v cc i/o1 v ss i/o8 to wp ce cle ale we re by / ry row address buffer decoder x the products described in this document are subject to the foreign exchange and foreign trade laws. x the information contained herein is presented only as a guide for the applications of our products. no responsibility is assume d b y toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from i ts use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation o r others. x the information contained herein is subject to change without notice. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 3/32 t c 5 8 n v g 0 s 3 a f t 0 0 valid blocks (1) symbol parameter min typ. max unit n vb number of valid blocks 1004 - 1024 blocks (1) the tc58nvg0s3a occasionally contains unusable blocks. refer to application note (13) toward the end of this document. (2) the first block (block address #00) is guaranteed to be a valid block at the time of shipment. recommended dc operating conditions symbol parameter min typ. max unit v cc power supply voltage 2.7 3.3 3.6 v v ih high level input voltage 2.0 v cc 0.3 v v il low level input voltage 0.3 * 0.8 v * 2 v (pulse width lower than 20 ns) dc characteristics (ta 0 to 70 ? , v cc 2.7v ~ 3.3 v) symbol parameter condition min typ. max unit i il input leakage current v in 0 v to v cc r 10 p a i lo output leakage current v out 0 v to v cc r 10 p a i cco1 reading ce v il , i out 0 ma, t cycle 50 ns 10 30 ma i cco7 programming current 10 30 ma i cco8 erasing current 10 30 ma i ccs1 standby current ce v ih , wp 0v/vcc 1 ma i ccs2 standby current ce v cc 0.2 v , wp 0v/vcc 50 p a v oh high level output voltage vcc, i oh 400 p a 2.4 v v ol low level output voltage vcc, i ol 2.1 ma 0.4 v i ol ( by / ry ) output current of by / ry pin v ol 0.4 v 8 ma www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 4/32 t c 5 8 n v g 0 s 3 a f t 0 0 ac characteristics and recommended operating conditions (ta 0 to 70 ? , v cc 2.7v ~ 3.6v) symbol parameter min max unit notes t cls cle setup time 0 ns t clh cle hold time 10 ns t cs ce setup time 0 ns t ch ce hold time 10 ns t wp write pulse width 25 ns t als ale setup time 0 ns t alh ale hold time 10 ns t ds data setup time 20 ns t dh data hold time 10 ns t wc write cycle time 50 ns t wh we high hold time 15 ns t ww wp high to we low 100 ns t rr ready to re falling edge 20 ns t rw ready to we falling edge 20 ns t rp read pulse width 35 ns t rc read cycle time 50 ns t rea re access time (serial data access) 35 ns t cea ce access time 45 ns t clea cle access time 45 ns t alea ale access time 45 ns t reaid re access time (id read) 35 ns t oh data output hold time 10 ns t rhz re high to output high impedance 30 ns t chz ce high to output high impedance 20 ns t reh re high hold time 15 ns t ir output-high-impedance-to- re falling edge 0 ns t rsto re access time (status read) 35 ns t csto ce access time (status read) 45 ns t clsto cle access time (status read) 45 ns t rhw re high to we low 30 ns t whc we high to ce low 30 ns t whr we high to re low 30 ns t cr ce low to re low (id read) 100 ns t r memory cell array to starting address 25 p s t wb we high to busy 200 ns t rst device reset time (read/program/erase) 6/10/500 p s www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 5/32 t c 5 8 n v g 0 s 3 a f t 0 0 ac test conditions parameter condition input level 2.4 v, 0.4 v input pulse rise and fall time 3ns input comparison level 1.5 v, 1.5 v output data comparison level 1.5 v, 1.5 v output load c l (100 pf) 1 ttl programming and erasing characteristics (ta 0 to 70 ? , v cc 2.7v ~ 3.6v) symbol parameter min typ. max unit notes t prog average programming time 200 700 p s n number of programming cycles on same page (per 512+16 bytes) 2 (1) t berase block erasing time 2 4 ms (1) refer to application note (12) toward the end of this document. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 6/32 t c 5 8 n v g 0 s 3 a f t 0 0 timing diagrams latch timing diagram for command/address /data command input cycle timing diagram cle ale ce re we hold time t dh setu p time t ds i/o1 to i/o8 : v ih or v il t cs t dh t ds t als t alh t wp t cls t ch t clh : v ih or v il ce cle we ale i/o1 to i/o8 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 7/32 t c 5 8 n v g 0 s 3 a f t 0 0 address input cycle timing diagram data input cycle timing diagram : v ih or v il we t wp t wp t wh t wp t als t wc t dh t ds d in 0 d in 1 t clh t ch ale cle ce i/o1 to i/o8 d in 2111 t dh t ds t dh t ds : v ih or v il t dh t ds t cls cle t als t alh t wp t wh t wp ca0 to7 t dh t ds ca8 to11 t cs t wc ce we ale t dh t ds t wp t wh pa0 to 7 t wc t dh t ds t wp t wh pa8 to 15 t wc i/o1 to i/o8 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 8/32 t c 5 8 n v g 0 s 3 a f t 0 0 serial read cycle timing diagram status read cycle timing diagram t reh t chz ce t rhz t rea t rc t rr t rhz t rea t rhz t rea re by / ry i/o1 to i/o8 t oh t oh t oh t rp t rp t rp t whr we t dh t ds t cls t clsto t cs t clh t ch t wp status output 70h* t whc t csto t ir t rsto t rhz t chz ce cle re by / ry i/o1 to i/o8 : v ih or v il t oh * 70h represents the hexadecimal number t cea www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 9/32 t c 5 8 n v g 0 s 3 a f t 0 0 read cycle timing diagram by / ry read cycle timing diagram : when interrupted by /ce by / ry t clea i/o1 to i/o8 t cs t cls t clh t ch 00h ca0 to 7 ca8 to 11 pa8 to 15 t dh t ds t wc t als t alh t r we cle ce ale re t dh t ds t dh t ds t dh t ds pa0 to 7 t dh t ds 30h t dh t ds t alh t wb t cs t cls t ch t als t rc d out n d out n 1 t rr t rea t cea col. add. n data out from col. add. n i/o1 to i/o8 we cle ce ale re t clea t cs t cls t clh t ch 00h t dh t ds t wc t als t alh t r t dh t ds t dh t ds t dh t ds t dh t ds 30h t dh t ds t alh t wb t cs t cls t clh t ch t als t rc d out n d out n 1 t rr t rea t cea t chz t rhz t oh ca0 to 7 ca8 to 11 pa8 to 15 pa0 to 7 col. add. n col. add. n www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 10/32 t c 5 8 n v g 0 s 3 a f t 0 0 column address change in read cycle timing diagram (1/2) by / ry t clea i/o1 to i/o8 t cs t cls t clh t ch 00h ca0 to 7 ca8 to 11 pa8 to 1 5 t dh t ds t wc t als t alh t r cle ce ale re t dh t ds t dh t ds t dh t ds column address a pa0 to 7 t dh t ds 30h t dh t ds t alh t wb t cs t cls t clh t ch t als t rc d out a d out a 1 t rea d out a n 1 t cea t rr continues to 1 of next page page address p page address p column address a www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 11/32 t c 5 8 n v g 0 s 3 a f t 0 0 column address change in read cycle timing diagram (2/2) we by / ry i/o1 to i/o8 t cs t cls t clh t ch 05h ca0 to 7 ca8 to 11 t wc t als t alh cle ce ale re t dh t ds t dh t ds t dh t ds column address b e0h t dh t ds t alh t cs t cls t clh t ch t als d out b d out b 1 t rea d out b n? 1 d out a n t rhw continued from 1 of last page page address p column address b t rc t clea t cea t ir www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 12/32 t c 5 8 n v g 0 s 3 a f t 0 0 auto-program operation timing diagram t cls t dh t cls t als t ds t dh t ds t dh ca0 to 7 80h we cle ce ale re by / ry t prog : v ih or v il t clh t ch t cs d in 0 d in 1 t wb 70h t ds t ds t dh t alh 10h i/o1 to i/o8 t alh t als d in 2111 status output : do not input data while data is being output. pa0 to 7 ca8 to 11 t cs pa8 to 15 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 13/32 t c 5 8 n v g 0 s 3 a f t 0 0 auto block erase timing diagram t cs 60h pa8 to 1 5 we cle ce ale re by / ry : v ih or v il t cls t clh t cls pa0 to 7 t ds t dh t als : do not input data while data is being output. d0h 70h t wb t berase busy status read command erase start command auto block erase setup command i/o1 toi/o8 status output t alh www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 14/32 t c 5 8 n v g 0 s 3 a f t 0 0 id read operation timing diagram : v ih or v il we cle re t cea ce ale i/o t alea id read command address 00 maker code device code 90h 00h t reaid 98h f1h t cls t cs tdh tdh t ch t alh t als t cls t cs t ch t alh t reaid t reaid t reaid t reaid note1 note2 note3 note1 : 80h or 00h note2 : 95h or 15h note3 : 40h or c0h www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 15/32 t c 5 8 n v g 0 s 3 a f t 0 0 pin functions the device is a serial access memory which utilizes time-sharing input of address information. the device pin-outs are configured as shown in figure 1. command latch enable: cle the cle input signal is used to control loading of the operation mode command into the internal command register. the command is latched into the command register from the i/o port on the rising edge of the we signal while cle is high. address latch enable: ale the ale signal is used to control loading of either address information or input data into the internal address/data register. address information is latched on the rising edge of we if ale is high. input data is latched if ale is low. chip enable: the device goes into a low-power standby mode when ce goes high during the device is in ready state. the ce signal is ignored when device is in busy state ( by / ry l ), such as during a program or erase or read operation, and will not enter standby mode even if the ce input goes high. write enable: the we signal is used to control the acquisition of data from the i/o port. read enable: the re signal controls serial data output. data is available t rea after the falling edge of re . the internal column address counter is also incremented (address = address + l) on this falling edge. i/o port: i/o1 to 8 the i/o1 to 8 pins are used as a port for transfe rring address, command and input/output data to and from the device. write protect: the wp signal is used to protect the device from acciden tal programming or erasing. the internal voltage regulator is reset when wp is low. this signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. ready/busy: the by / ry output signal is used to indicate the operating condition of the device. the by / ry signal is in busy state ( by / ry = l) during the program, erase and read operations and will return to ready state ( by / ry = h) after completion of the operation. the output buffer for this signal is an open drain and has to be pulled-up to vccq with appropriate resister.. ce we re wp by / ry 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 nc nc nc nc i/o8 i/o7 i/o6 i/o5 nc nc nc v cc v ss nc nc nc i/o4 i/o3 i/o2 i/o1 nc nc nc nc nc nc nc nc nc gnd nc nc v cc v ss nc nc cle ale nc nc nc nc nc we by / ry 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 wp re ce figure 1. pinout www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 16/32 t c 5 8 n v g 0 s 3 a f t 0 0 schematic cell layout and address assignment the program operation works on page units while the erase operation works on block units. a page consists of 2112 byte s in which 2048 bytes are used for main memory stor age and 64 bytes are for redundancy or for other uses. 1 page = 2112bytes 1 block = 2112 bytes x 64 pages = (128k + 4k) bytes capacity = 2112bytes x 64pages x 1024blocks an address is read in via the i/0 port over four consecutive clock cycles, as shown in table 1. table 1. addressing i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 first cycle ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second cycle l l l l ca11 ca10 ca9 ca8 third cycle pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ca0 to ca11 : column address pa0 to pa15 : page address pa6 to pa15 : block address pa0 to pa5 : nand address in block fourth cycle pa15 pa14 pa13 pa12 pa11 pa10 pa9 pa8 operation mode: logic and command tables the operation modes such as program, erase, read and reset are controlled by the eleven different command operations shown in table 3. address input, command input and data input/output are controlled by the cle, ale, ce , we , re and wp signals, as shown in table 2. table 2. logic table cle ale ce we re wp * 1 command input h l l h * data input l l l h h address input l h l h * serial data output l l l h * during programming (busy) * * * * * h during erasing (busy) * * * * * h during reading (busy) * * * * * * program, erase inhibit * * * * * l standby * * h * * 0 v/vcc h: v ih , l: v il , * : v ih or v il * 1: refer to application note (10) toward the end of this document regarding the wp signal when program or erase inhibit 65536 pages 1024blocks figure 2. schematic cell layout 64pages = 1block 8i/o 2112 i/o1 i/o8 64 2048 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 17/32 t c 5 8 n v g 0 s 3 a f t 0 0 table 3. command table (hex) first cycle second cycle acceptable while busy serial data input 80 auto program 10 read address input 00 column address change in serial data output 05 read start 30 read column change e0 auto block erase 60 d id read 90 status read 70 reset ff table 4 shows the operation states for read mode. table 4. read mode operation states cle ale ce we re i/o1 to i/o8 power output select l l l h l data output active output deselect l l l h h high impedance active standby l l h h * high impedance standby read busy ***** high impedance active h: v ih , l: v il , * : v ih or v il 1 0 0 0 0 0 0 0 i/o8 7 6 5 4 3 2 i/o1 serial data input : 80h hex data bit assignment (example) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 18/32 t c 5 8 n v g 0 s 3 a f t 0 0 device operation read mode read mode is set when "00h" and ?30h? commands are issued to the command register. between the commands, start address for the read mode need to be issued. refer to figure 3 below for sequence and the block diagram (refer to the detailed timing chart.). random column address change in read cycle re start-address input a data transfer operation from the cell array to the registe r starts on the rising edge of we in the 30h command input cycle (after the address information has been latched). the device will be in busy state during this transfer period. after the transfer period the device returns to ready state. serial data can be output synchronously with the re clock from the start address designated in the address input cycle. by / ry we cle re 00h ce ale i/o busy 30h page address n column address m m m+1 m+2 page address n cell array select page n m figure 3. read mode (1) operation 2111 start-address input in the serial data out from the register, the column address can be changed by inputting the column address with 05h and e0h commands. the data are read out in serial from the column address which is input to the device by 05h and e0h commands with /re clock. by / ry we cle 00h ce ale i/o busy page n 30h 05h e0h col. m page n col. m? m m+1 m+2 m+3 m? m?+1 m?+2 m?+3 m?+4 page n figure 4. random column address change in serial read cell array select page n m m? col. m start from col. m start from col. m? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 19/32 t c 5 8 n v g 0 s 3 a f t 0 0 auto page program operation the device carries out an automatic page program operation when it receives a "10h" program command after the address and data have been input. the sequence of command, address and data input is shown below. (refer to the detailed timing chart.) re by / ry auto block erase the auto block erase operation starts on the rising edge of we after the erase start command ?doh? which follows the erase setup command "60h". this two-c ycle process for erase operat ions acts as an extra layer of protection from accidental erasure of data due to external noise. the device automatically executes the erase and verify operations. the data is transferred (programmed) from the register to the selected page on the rising edge of we following input o f the ? 10h command. after programming, the programmed data is transferred back to the register to be automatically verified by the device. if the programming does not succeed, the program/verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. cle 80h ale i/o din page p 10h 70h /ce /we din din din col. m data status out figure 7. auto page program operation data input selected page readin g & verification program pass i/o fail by / ry 60 d0 70 block address input : 2 cycles status read command busy erase start command www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 20/32 t c 5 8 n v g 0 s 3 a f t 0 0 id read the device contains id code which identify the devi ce type, the manufacturer, and some features of the device. the id codes can be read out under the following timing conditions: table 6. code table descripton i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data 1 st data maker code 1 0 0 1 1 0 0 0 98h 2 nd data device code 1 1 1 1 0 0 0 1 f1h 3 rd data chip number, cell type, pgm page 0 or 1 0 0 0 0 0 0 0 80h or 00h 4 th data page size, block size, redundant size, organization 0 or 1 0 0 1 0 1 0 1 95h or 15h 5 th data plane number, plane size 0 or 1 1 0 0 0 0 0 0 40h or c0h 3 rd data descripton i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 1 0 0 2 01 4 10 internal chip number 8 11 2 level cell 0 0 4 level cell 0 1 8 level cell 1 0 cell type 16 level cell 1 1 100 2 01 4 10 number of simultaneously programmed pages 8 11 reserved 1 0 reserved 2 0 or 1 fi gure 13 . id r ea dti m i ng for the specifications of the access times t reaid, t cr and t alea refer to the ac characteristics. we cle re t cea ce ale i/o t alea t reaid id read command address 00 maker code device code 90h 00h 98h f1h note1 note2 note3 note1 : 80h or 00h note2 : 95h or 15h note3 : 40h or c0h www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 21/32 t c 5 8 n v g 0 s 3 a f t 0 0 4 rd data descripton i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 1kb 0 0 2kb 01 4kb 10 page size (without redundant area) 8kb 11 64kb 00 128kb 01 256kb 10 block size (without redundant area) 512kb 11 80 0 16 0 1 reserved 1 0 redundant area size (byte/512byte) reserved 1 1 x8 0 organization x16 1 reserved 0 or 1 5 th data descripton i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 1 0 0 2 0 1 4 1 0 plane number 8 1 1 64mb 000 128mb 001 256mb 010 512mb 011 1gb 1 0 0 2gb 101 4gb 110 plane size 8gb 111 reserved 0 or 1 0 0 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 22/32 t c 5 8 n v g 0 s 3 a f t 0 0 status read the device automatically implements the execution and verification of the program and erase operations. the status read function is used to monitor the ready/busy status of the device, determine the result (pass /fail) of a program or erase operation, and determine whether the device is in protect mode. the device status is output via the i/o port on the re clock after a ?70h" command input. the resulting information is outlined in table 5. table 5. status output table status output i/o1 chip status 1 pass: 0 fail: 1 i/o2 not used 0 or 1 i/o3 not used 0 i/o4 not used 0 i/o5 not used 0 i/o6 ready/busy ready: 1 busy: 0 i/o7 not used 0 or 1 i/o8 write protect protect: 0 not protected: 1 the pass/fail status on i/o1 is only valid when the device is in the ready state. an application example with multiple devices is shown in figure 6. system design note: if the by / ry pin signals from multiple devices ar e wired together as shown in the diagram, the status read function can be used to determine the status of each individual device. device 1 cle 1 ce device 2 2 ce device 3 3 ce device n n ce device n 1 1 n ce ale we re i/o1 to i/o8 by / ry we re status on device 1 70h 1 ce ale i/o 70h status on device n by / ry cle n ce figure 6. status read timing application example busy www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 23/32 t c 5 8 n v g 0 s 3 a f t 0 0 reset the reset mode stops all operations. for example, in the case of a program or erase operation the internally generated voltage is discharged to 0 volts and the device enters wait state. the response to an "ffh" reset command input during the various device operations is as follows: when a reset (ffh) command is input during programming when a reset (ffh) command is input during erasing when a reset (ffh) command is input during read operation when a status read command (70h) is input after a reset when two or more reset commands are input in succession internal v pp 80 10 ff figure 8. 00 by / ry t rst (max 10 p s) internal erase voltage d0 ff figure 9. 00 by / ry t rst (max 500 p s) 00 ff figure 10. 00 by / ry t rst (max 6 p s) 10 figure 12. by / ry ff ff (3) (2) (1) the second command is invalid, but the third command is valid. ff ff ff 30 ff 70 by / ry i/o status : pass/fail o pass : ready/busy o ready figure 11. ff 70 by / ry i/o status : ready/busy o busy www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 24/32 t c 5 8 n v g 0 s 3 a f t 0 0 application notes and comments (1) power-on/off sequence: the timing sequence shown in figure 15 is necessary for power-on/off sequence. the device internal initialization start after the power supply reaches appropriate level in power on sequence. during the initialization the device ready/busy si gnal outputs busy st ate as shown in the figure-15. in this time period, th e acceptable commands are ffh or 70h. the wp signal is useful for protecting agai nst data corruption at power-on/off. (2) status after power-on the following sequence is necessary because some input signals may not be stable at power-on. (3) prohibition of unspecified commands the operation commands are listed in table 3. input of a command other than those specified in table 3 is prohibited. stored data may be corrupted if an unknown command is entered during the command cycle. (4) restriction of command while busy state during busy state, do not inpu t any command except 70h, and ffh. v il operation 0 v v cc 2.7v 2.5v v il don?t care don?t care figure 15. power-on/off sequence v ih ce , we , re wp cle, ale invalid don?t care ready/bus y 1ms max 100s max ff reset power on figure 16. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 25/32 t c 5 8 n v g 0 s 3 a f t 0 0 (5) acceptable commands after serial input command "80h" once the serial input command "80h" has been input, do not input any command other than the column address change in auto program command "10h? or the reset command "ffh". if a command other than "10h" or "ffh" is input, the program operation is not performed and the device operation is set to the mode which the input command specifies.. (6) addressing for program operation within a block, the pages must be programmed consecutively from the lsb (least significant bit) page of the block to msb (most significant bit) page of the block. random page address programming is prohibited. command other than "10h" or ?ffh? 80 programming cannot be executed. 10 xx we by / ry 80 ff address input mode specified by the command. data in: data (1) page 0 data register page 2 page 1 page 31 page 63 (1) (2) (3) (32) (64) data (64) from the lsb page to msb page data in: data (1) page 0 data register page 2 page 1 page 31 page 63 (2) (32) (3) (1) (64) data (64) ex.) random page program (prohibition) figure 17. page programming within a block www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 26/32 t c 5 8 n v g 0 s 3 a f t 0 0 (7) status read during a read operation the device status can be read out by inputt ing the status read command ?70h? in read mode. once the device has been set to status read mode by a ?70h? command, the device will not return to read mode. therefore, a status read during a read operation is prohibited. however, when the read command ?00h? is input during [a], status mode is reset and the device returns to read mode. in this case, data output starts automatically from address n and address input is unnecessary (8) auto programming failure (9) by / ry : termination for the ready/busy pin ( by / ry ) a pull-up resistor needs to be used for termination because the by / ry buffer consists of an open drain circuit. fail 80 10 80 10 address m data input 70 i/o address n data input if the programming result for page address m is fail, do not try to program the page to address n in another block without the data input sequence. because the previous input data has been lost, the same input sequence of 80h command, address and data is necessary. 10 80 figure 19. m n this data may vary fr om device to device. we recommend that you use this data as a reference when selecting a resistor value. v cc v cc device v ss r by / ry c l 1.5 p s 1.0 p s 0.5 p s 0 1 k : 4 k : 3 k : 2 k : 15 ns 10 ns 5 ns t f t r r t r t f v cc 3.3 v ta 25c c l 100 pf figure 19. t f ready 3.0 v v cc 1.0 v t r 3.0 v 1.0 v busy 00 address n comman ce we by / ry re [a] status read command input status read status output figure 18. 70 00 30 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 27/32 t c 5 8 n v g 0 s 3 a f t 0 0 (10) note regarding the wp signal the erase and program operations are automatically reset when wp goes low. the operations are enabled and disabled as follows: enable programming disable programming enable erasing disable erasing wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 28/32 t c 5 8 n v g 0 s 3 a f t 0 0 (11) when five addre ss cycles are input although the device may read in a fifth address, it is ignored inside the chip. read operation program operation figure 22. cle address input 00h ce we ale i/o by / ry ignored 30h cle ce we ale i/o figure 23. address input ignored data input 80h www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 29/32 t c 5 8 n v g 0 s 3 a f t 0 0 (12) several programming cycles on th e same page (partial page program) a page can be divided into up to 8 segments as follows :- data area (column address 0 to 2047) : 512 bytes x 4 segments 1 st segment: column address 0 to 511 2 nd segment: column address 512 to 1023 3 rd segment: column address 1024 to 1535 4 th segment: column address 1536 to 2047 redundant area (column address 2 048 to 2111) : 16 bytes x 4 segments 1 st segment: column address 2048 to 2063 2 nd segment: column address 2064 to 2079 3 rd segment: column address 2080 to 2095 4 th segment: column address 2096 to 2111 . each segment can be progra mmed individually as follows: note: the input data for unprogrammed or previously programmed page segments must be "1" (i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all ?1?). data pattern 8 data pattern 1 all 1s all 1s all 1s all 1s figure 24. 1st programming 2nd programming 8th programming result data pattern 1 data pattern 2 data pattern 8 data pattern 2 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 30/32 t c 5 8 n v g 0 s 3 a f t 0 0 (13) invalid blocks (bad blocks) the device occasionally co ntains unusable blocks. therefore, the following issues must be recognized: at the time of shipment, all data bytes in a valid block are ffh. for bad blocks, all bytes are not in the ffh state. please don?t perform erase operation to bad blocks. check if the device has any bad b locks after installation into the system. figure 27 shows the test fl ow for bad block detection. bad blocks which are detected by the test flow must be managed as unusable blocks by the system. a bad block does not affect the performance of good blocks because it is isolated from the bit line by the select gate the number of valid blocks at the time of shipment is as follows: min typ. max unit valid (good) block number 1004 - 1024 block bad block test flow bad block bad block figure 26. read check : read the 1st page or the 2nd page of each block. if the column address 0 or 2048 of the 1st page or the 2nd page is not ff (hex), define the block as a bad block. pass read check start bad block *1 block no. 1024 end yes fail block no 1 no block no. block no. 1 ????6?,9(:,?67,9(;065?0:?(336>,+?;6?+,;,*;,+?)(+?)36*2:? figure 27. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 31/32 t c 5 8 n v g 0 s 3 a f t 0 0 (14) failure phenomena for program and erase operations the device may fail during a program or erase operation. the following possible failure modes should be considered when implementing a highly reliable system. failure mode detection and countermeasure sequenie block erase failure status read after erase o block replacement page programming failure status read after program o block replacement (1) block verify after program o retry single bit programming failure ? 1 to 0 ? (2) ecc x ecc : error correction code . x block replacement program erase when an error occurs in an erase operatio n, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) do not turn off the power before write/erase operation is complete. avoid using the device when the battery is low. power shortage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data. when an error happens in block a, try to reprogram the data into another block (block b) by loading from an external buffer. then, prevent further system accesses to block a ( by creating a bad block table or by using another appropriate scheme). block a block b error occurs buffer memory fi g ure 27. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2003-02-25a 32/32 t c 5 8 n v g 0 s 3 a f t 0 0 package dimensions weight: 0.53 g (typ.) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com

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